The microelectronic industry is continually striving to produce ever faster and smaller microelectronic devices for use in various electronic products, including, but not limited to portable products, such as portable computers, digital cameras, electronic tablets, cellular phones, and the like. An example of one such microelectronic device is a mobile chip scale package, which is well known in the art. Non-embedded trace substrates may be used in the formation of coreless substrates for such mobile chip scale packages. Non-embedded trace substrates are generally formed with modified semi-additive processes which result in protruding traces. However, such protruding traces may suffer from sidewall etching, as known to those skilled in the art. Thus, embedded trace substrates have become prevalent in the formation of coreless substrates for such chip scale packages. These embedded trace substrates can enable very fine line/space patterning, which can translate into high input/output density, compared with traditional non-embedded trace substrates due to the fact that embedded traces do not suffer from sidewall etching.
Although embedded trace substrates have further advantages, such as high trace reliability and good substrate surface flatness, they do present a key challenge with regard to misalignment during subsequent microelectronic device placement/attachment. This misalignment is due to the fact that the embedded traces may be recessed below surrounding dielectric material of the coreless substrate, which may cause such misalignment, as will be understood to those skilled in the art. Therefore, there is a need for a trace structure, which has the advantages of embedded traces without a risk of microelectronic device placement/attachment misalignment.